1. Field of the Invention
The present invention relates to data processing systems and more particularly to apparatus for isolating errors within a data processing system which includes a multiport memory system.
2. Description of the Prior Art
It is well known to include apparatus within a data processing system for diagnosing which subsystem within a system has failed. Generally, the subsystems are required to connect to and share common interfaces and buses.
Systems have been provided for testing subsystems which connect to a memory system via a common system bus. A first such system is disclosed in U.S. Pat. No. 4,159,534 entitled "Firmware/Hardware System for Testing Interface Logic of a Data Processing System". In this system, means are provided for testing bus interface logic circuits of the subsystem by generating incorrect memory address on the common system bus. This prevents the memory system from acknowledging the address while permitting the data applied to the bus by the subsystem to be returned to the subsystem's input registers for comparison. This system has been found to provide limited isolation capabilities. That is, a malfunction of the common system bus or the memory system could also produce the detected error condition.
Another data processing system has provided an arrangement for testing a data path between the registers of a processing unit at a local common bus interface and internally within the processing unit. This arrangement is disclosed in the copending patent application of Virenda S. Negi and Steven A. Tague entitled "Diagnostic Testing of the Data Path in a Microprogrammed Data Processor", Ser. No. 06/250,820, filed on Apr. 3, 1981 and assigned to the same assignee as named herein. The data path is tested by transferring different combinations of data signals having good and bad parity through the registers within the established path and comparing the input and output data signals. While the arrangement verifies the established data path between registers, it is still not possible to isolate the error condition between the common bus and the other subsystems or units which connect to the common bus.
While the above prior art systems are able to diagnose specific types of errors or faults within certain subsystems, these systems normally include memory systems in which data and address paths located on a main board are connected in common with the data and address paths of the memory modules or pacs, all of which are contained on separate memory boards. The diagnostic procedure for testing the data and address paths has been to include diagnostic software which generates read and write memory commands for addressing different locations within the different memory modules writing known patterns there and reading them out. If the data and address paths, in addition to the memory module, are operational, the patterns will match. If anything within the paths or module has failed, a mismatch will occur. When it does, it still is not possible to isolate the error to the memory board of memory module being addressed or to the main board address and data paths.
Because of greater accessability, similar, more extensive programs employed for factory testing have utilized similar testing procedures. While in this type of testing environment, it is easier to isolate the problem area, it still is difficult to access certain boards for probing within an assembled system.
Accordingly, it is a primary object of the present invention to provide an arrangement which allows faults or errors within a data processing system to be isolated with greater specificity and ease.
It is a further object of the present invention to include a minimum of additional apparatus within a system for diagnosing faults within the replaceable units or subsystems associated with memory system.